Digital electronics
Previous year question paper with solutions for Digital electronics May-2017
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Question paper 1
SECTION-A
1.(a) Find I’s and 2’s complement of the following 8-digit binary numbers :10101110; 10000001; 10000000; 00000001 and 00000000.
Answer:
Find 1’s and 2’s Complement of the following 8-digit binary numbers :
10101110; 10000001; 10000000; 00000001; and 00000000 .
Q1=> 10101110
10101110 Binary no
01010001 1’s complement
01010000 2,’s Complement
Q2=>10000001 Binary no
01111110 1’s Complement
+1
01111111 2’s Complement
Q3=> 10000000 Binary no
01111111 1’ Complement
+1
100000000 2’ Complement
Q=>4 00000001 Binary no
11111110 1’s Complement
+1
11111111 2’s Complement
Q=>5 00000000 Binary no
11111111 1’s Complement
+1
00000000 2’ Complement
1 Carry
Q3 1’s Complement
(i)10101110 01010001
(ii)10000000101111110
(iii)1000000001111111
(iv)0000000111111110
(v)0000000011111111
(b) Explain POS and SOP from of expressions.
Answer:
Explain Pos and Sop Form of expressions.
Product of Sum (Pos) =>
When two a sum termal are multiplied by Boalean Multiplication the resulting expression is termed as product of sum.
Example=>
(1)(A+B).(A+)
(2)(A+B).(B+C+.(
(3)B(A+B).(A+C) etc.
Every POS expression can be imp complement by simply adding the out puts of two or gates there force Pos expression can be implemented by Or-AIVI) realization like sop expression Pos expression cam also be implemented by Universal gates for example ->
Of AIOP and Nor- Nor crealization POS expression U = (A+C) (A+B+C)
Y=(A+C)
(A+B+C).(B+C)
=(A+C)+(A+B+C)+(B+C)
Q2. Perform the following numbers conversions :
(i)
(ii)
(iii)
(iv)
(v)
(vi)
(vii)
(viii)
Answer:
(i) (3FEF
(3FEF=(15275 Ans.
(ii)
F 4 3 2
1111 0100 0011 0010
=(1111 0100 0011 0010 Ans.
(iii)
Octal Number ->
(65=(110101 Ans.
(v)(B3D8
B3D8->(1011 0011 1101 1000)
00 011 001 111 011 000
1 3 1 7 3 0
B3D8=(31730
(vi)
(vii)
(+ ( + ( + (
0.25+0.6875+0.75+(0.0507812)
(AB.CD=(2.1132512 ans.
(viii)
7 2 2 2 <- Octal
111 010 010 010<- Binary QUICLER OF OCTAL
4(a) Show that NAND gates are universal gates.
Answer:
NAND gate=> The Combination of Not- AND Gates is know as the NAND gate The output of the NAND gate is complemented inverted as show in Fig 3.10(a)
Digram
NAND gate have two or more inputs and single out put the logical symbol 2 = input NAND gat is show in Fig 3.10
If A and B are the inputs of NAND gate then the output Y is AB or A NAND B the troth table of NAND gate is shown in table 3.5
Inputs
Outputs of AND gate
Final Output
A
B
Y=AB
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
Inputs
Outputs
A
B
Y=AB
0
0
1
0
1
1
1
0
1
1
1
0
Sol= Show NAND gate as Universal gate:
As Already discussed in Section that the NAND gate is Universal gate I e, the there basic logic operations ( AND, OR, and NOT ) can be performed by using only.
(i) NAND gate as a Not gate is shown in Fig 3.12
Digram
(ii) NAND gate as AND gate:
Digram
(iii) NAND gate a or gate:
Digram
(b)Distinguish between analog and digital circuits.
Answer:
Difference b/w analog and digital circuits.
Analog representation=> The Numerical representation in which a quantity is represented by a voltage or Current analog voltage or Circuits or b/w defined values
Digital representation=> The Numerical representation in which a Quantity is by the symbol called digital Voltages is assents can very only by discs steps
SECTION-B
Q5.(a) Construct a 4x16 decoder using two 3x8decoders.
Answer:
decoder => it will accept three inputs and produce eight outputs.
A
B
C
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
1
0
0
0
0
0
1
0
0
1
1
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
1
Decoder=> it will accept the foes input and produce the 16 output.
A
B
C
D
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
1
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
(b) Explain the working principle of Master slave flip flops.
Answer:
A Master slave jk flop can be coos using two se gap flop se ally with feedback from the outputs of the second SR-FA to the inputs of the first ore it is hand to as the spa and the first flip flop saver as the master to as master slave (m .s) lip Frap positive clock pulse are applied to the master flip flop are the positive clock pulses are applied to the slave flip flop.
When clk=1 master is enabled and it follow troth table of JK FF but dosing this time
S lowe is
(does not respord )
When Clk =o slave is enabled and the master is inhibited therefore the outputs of slave flip flop follow the output of master flip flop but using this time master does not respond this the sace around condition dors not exit I this circuit we conclude that when master is working slave is not and so the output of slave flip flop cannot be feedback is between the clock pluse there fore the race Ground condition does not exist simiilasly when slave is working the output feedback is since master flip flop is inhibited, so the problem of Change of input dosing the clock is auto matically slaved
6.(a)How can you realize the edge triggered J-K Flip Flop from an S-R Flip Flop?
Answer:
Truth table of JK flip flop=> SR-FF when the inputs are (S=R=1) we could not get propes output since it produces or under next stage and was dis allowed this under makes the SRFF difficult to manage and there fie it is not used is active the JK flip flop eliminated this difficulty SR FF can be can into JK FF b AND the Q and Q outputs of SR FF with J and K inputs.
All the possible comb nation of J and K inputs and for each comp nation both the states (0 0 1) of the output let us the final output be and then the output stage will be and
Inputs
Post output
Input to SREE
OutPut
0
0
0
1
0
0
0
0
0
1
0
0
0
1=
0
1
0
1
1
0
1
0
1
1
0
0
0
1=1
1
0
0
1
0
0
0
1
0
1
0
0
1
0=0
1
1
0
1
1
0
1
1
1
1
0
0
1
Truth table of JK FF
Input
Output
0
0
0
1
0
1
0
1
1
1
It show that input K=K=1 produces the complement of post valve in the output.
Logic symbol of JK-FF.
(b) Write the truth table of J-K Flip Flop and explain how race-around problem can be solved in it.
Answer:
Race around problem of JK FF=> The race around condition when J=K =1 In JK=FF, the output is feedback to of the input and these fore change in the output results change in the input.
Let for example the inputs J=K and 2=0and a clock pulse with width at the clock input after a the internal it the output will change to 2=1 now (after it ) we have J=K =1 and 2-1 and after another time internal of it the output will change back to d=0 Hence the output will oscillate back and forth between 0 and 1 for the dosation of the clock pulse At the and of click pulse the valve of is unccstain this seduction is know as race around condition.
The race around condition can be using following ways.
-
If to
-
Edge Triggsing flep flop
-
Master slave JK FF
First way of race around condition way be difficult because to make the clock Plus of very small frequency become costly and difficult Edge Triggering flip flop however is Covered in section.
-
Q7.(a)Draw the circuit of an S-R Flip Flop using NOR gates only from it derive the circuit of a D- Flip Flop and explain its truth table.
Answer:
SR Flip Flop => The simplest single bit memory device is the set reset flip flop SRFF can be formed bit using NAND or NDR gates as (a) B respectively
Truth table of SR
S
R
0
0
0
1
1
0
1
1
Input
Output
Q
Depend upon pest valves
0 Re set
1 set
? (Disallowed)
(b) Draw the circuit of a 2 to 4 decoder and explain its function
Answer:
De coder (2 lines to 4 line)
Block diagram
Truth table of
Enable
Inputs
Outputs
E
A
B
1
0
0
1
0
0
0
1
0
1
0
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
1
8.(a)Explain the following:-
(i)What is the expression relating the output and inputs DAC?
(ii) Define step size of DAC.
(iii) Define full scale.(iv) Define percentage resolution.
Answer:
A digital to analog Convertor (DAC) is a device that converts digital numbers (binary) into An analog or Currant voltage or output An electronic device after an itc gsated circuit that converts a digital number into a analog Voltage as Current.
(ii)Define step size of DAC=> The Voltage difference between one digital level and the next one is called the step size
(iii)Define Full scale=> Full scale or full represents the maximum Amplitude a system can represent In digital systems a signal is said to be at digital full scale when its has reached the maximum representable value
(iv)Define percentage resolution=> Al though resolution can be expressed as the amount of voltage or current step it is also use full to express it as a percentage of the full scale output to Illustsate the step size is 1v, which gives a bessen stage resolution.
(b)Explain the working of DAC.
Answer:
Explain the working of DAC.
D/P Convssion is the process of taking A value represented in digital code (Such as straight binary DAC) and consisting it to a voltage as current which is proportional to the digital value Diagram shows the symbol for a typical 4- bit Now we will Examine the various input output relationships.
The digital input D, C, B and A are usually des from the output register of a digital system the 14=16 different binary numbers represented by these 4 bits for each input numbers the D/A conver output voltage is a unique value In fat for this case the analog output voltage is equal in volts to the binary number.
In general
Analog output K digital input
Where K is the proportionality factor and it is constant valve for a given DAC the analog Output an of voltage K will be in voltage units for the DAC of K=1, v so that
We can use this to for any value of digital input for example with a digital input of we optain
Digital systems and computes Organization .
SECTION-C
9.(a)Which is better among the 1’s and 2’s complement forms of the negative numbers?
Answer:
2’s Complement the Primary of two’s Complement over one’s Complement is that two’s Complement only has one value for Zero.
One’s Complement has a Positive Zero and a negative Zoo these by increasing usage
(b) Simplify the Following expression using Boolean algebra:
Answer:
=(C+D)’+ACD’+(A’+B’+C’)+ABCD ACD
=C’D’+A’CD’+A’+B’+C+ABCD’+ACD’
=C’D’+CD’(A’+A)+A’+B’+C’+ABCD’
= C’D’+CD’_A’+B’+C’
=D’(C’+C)+A’+B’+C’
=D’+A’+B’+C’
(c) Perform the following additions using 2s complement :
(i) -20 to +26
(ii) 25 to -15
Answer:
(i) -20 to +26
20=10100
1’s complement 01011
2’s complement -20 =01100
26=11010
01100
11010
00110 => 00110
=>4+2
=>6 ans.
(ii) 25 to -15
25=11001
-15=01111
1’s Complement 10000
2’s Complement -15=10001
10000
11001
01010 01010
=>10 ans.
(d)What is the need of A/D and D/A converters ? Justify with suitable examples.
Answer:
Micro processors can only De for comblex processing on digitized signals
When signals are in digital form they are less to the deleterious effects of additive noise.
ADC Provides link between the analog world transduces and the digital world of signal processing and data barding .
(e)What are Min and Max terms ?
Answer:
(i) Min => A Minter is a product (AND) of all Variables in the function in direct or Complemented form (2) Max term => has the pro that it is equal to 0 exactly one sun of the table.