Digital electronics
Previous year question paper with solutions for Digital electronics May-2018
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Question paper 1
SECTION-A
1. (a) Find 1’s and 2’s complement of the following 8-digit binary numbers : 10101110, 10000001, 10000000, 00000001 and 00000000.
Answer:
Find 1’s and 2’s complement of the following 8-digit binary numbers.
-
10101110
10101110
1’s Complement=> 01010001
2’s Complement=> +1
01010010
-
10000001
10000001
1’s Complement=> 01111110
+1
2’s Complement=> 01111111
-
10000000
1’s Complement => 01111111
+1
2’s Complement 10000000
-
00000001
1’s Complement => 11111110
+1
2’s Complement => 11111111
-
00000000
1’s Complement => 11111111
+1
2’s Complement =>00000000
-
(b) Simplify the expression
Answer:
Simplify the expression
The pro to Slow is z=(0)
So the theses don’t balance in the input
Final answer is 0.
2. (a) Using 2’s complement notation perform the following arithmetic operations using 8 bit register:
-
25 + (-12)
-
17-6
-
-18 -16
-
-8 + (18)
-
12- (-19)
Answer:
Using 2’s Complements notation perform the following arithmetic operation using 8 bit registers.
-
25+(-12)
25=00011001
12=00001100
Complement 1’s 11110011
+1
2’s Complement(-12) 11110100
00011001
11110100
00001101
00001101
8+4+1=>13 ans.
-
17-6
17=>00010001
6=>00000110
1’s Complement 11111001
+1
11111010
00010001
11111010
00001011
00001011
8+2+1
11 Ans.
-
-18-16
18=> 010010
101101
+1
(-18) 101110
16=> 010000
101111
-16=> 110000
101110
011110
011110
100001
+1
100010
=>32+2
=>34
-34 Ans.
(iv) -8+(18)
8=>1000
0111
+1
2’s Complement-8 1110
18=> 10010
-8+(18)=> 01000
10010
11010
00101
1
00110
8+2 => 10
10 ans.
(V) 12-(-19)
12=>01100
19=>10011
12-(-19)=>
01100
10011
11111
11111
16+8+4+2+1
31 Ans.
-
(b) Explain the working of XOR gate. Explain the role of XOR gate in parity generation.
Answer:
XOR gate is a digital logic gate that gives a tree Output when the numbers of true Output is Odd An XOR Hate Implements as Exclusive or that is a true Output results if one and only one of the inputs to the gate is true if both inputs are both are true if false output results XOR represents the is equality for action i. e the output is true if the inputs are not a like the output is false A way to remember XOR is Must have One as the other bot not both.
Input
Output
A
B
A XOR B
0
0
0
0
1
1
1
0
1
1
1
0
3.Simplify the expression:
Using K-map in POS form and represent the resulting function using NOR gates.
Answer:
Using K-map in POS form and represent the resulting for Action using NOR gates
A
B
C
D
F
0
0
0
0
0
1
0
0
0
1
1
0
0
0
1
0
2
1
0
0
1
1
3
0
0
1
0
0
4
0
0
1
0
1
5
0
0
1
1
0
6
0
0
1
1
1
7
0
0
0
0
0
8
1
1
0
0
1
9
1
1
0
0
10
1
1
0
1
1
11
1
1
1
0
0
12
0
1
1
0
1
13
0
1
1
1
0
14
1
1
1
1
1
15
0
-
1st & 2nd Ron of 2nd & 3rd column
=>
=>
=>
=>
(ii) 2nd Ron of will Column
=>
=>
=>
=>
=>
(iii)2nd & 3rd Run of 1st +& 2nd column
=>
=>
=>
=>B(
(iv)2nd & 3rd Run of 2nd and 3rd Colum
=>
=>
=>ABD+ABD
=>BD(
=>BD
Compliment both side
-
4. Fill in the blanks marked by ‘?’
Binary
Octal
Hexadecimal
Decimal
10101111
?
?
?
?
4567
?
?
?
?
AB.CD
?
?
?
?
1234
Answer:
(i) 10101111 to Decimal
-
10101111
=>(175)
(ii) Binary to Octal
=>(275
(iii)
A F
=>AF
(ii) 4567
-
Octal to binary
4 5 6 7
000 101 110 111
=>000101110111
(ii) Octal to Hexadecimal
177
(iii)Octal to Decimal
4 5 6 7
2048+320+48+7
=>2423
(iii) AB.CD
(i)Hexadecimal to binary
A B C D
=>10101011 . 10001101
(ii)Hexadecimal to Octal
=>253 . 432
(iii)Hexadecimal to Decimal
A B C D
10 11 12 13
160+11 . 0.75 +0.05
=>171.0.80
(iv)1234
(i)Decimal to binary
2
1234
2
617
2
308
2
154
2
77
2
38
2
19
2
9
2
4
2
2
1
10011010010
8
1234
8
154
2
8
19
2
2
3
(ii)Decimal to Octal
=>2322
(iii)Decimal to Hexadecimal
16
1234
16
77
2
4
13
4D2
-
5. (a) Explain the working of J-K flip flop in derail.
Answer:
JK flip flop is the modified version of SR flip flop H operates with only positive clock transitions as negative clock transitions the diagram of JK flip flop is shown in the following Fig
This circuit for two inputs J&K and two output the operation of JK flip flop is similar to SR flip flop Here we the inputs of SR flip flop as S=J and R=k t in order to utilize the modified SR flip flop for 4 of inputs the following table shows the state table of JK flip flop.
J K
0 0
0 1
0
1 0
1
1 1
Here t&are preset state & next state respectively So JK flip flop Can be used for one of these for function when positive transaction of clock signal applied the following table shows the characteristic table of JK flip flop.
Present In
Present Stale
Next stale
J K
0 0
0
0
0 0
1
1
0 1
0
0
0 1
1
0
1 0
0
1
1 0
1
1
1 1
0
1
1 1
1
0
By using there variable K-map we can get the Simplified expression for next stale three variable K map for next sate is shown the following
The maximum Graping of adjacent ones are already show in the figure there fore the simplified expression for next state is
(b) Distinguish between:
(i) Level clocking and Edge triggering
(ii) De-multiplexer and Decoder.
Answer:
Distinguish between
(i) Level clocking and Edge triggering
Level Clocking
Edge triggering
1.Level allows a circuit to become active at when the clock pulse is on a has ticulas level.
1.Eage triggering allows a circuit to become active at the positive edge or the negative edge of the clock signal
2. An event occurs during the high voltage level or low voltage level.
2. An event Occurs at the sis ting edge or following edge
3. Latches are level trigged
3. Flip flops are edge triggered.
(ii)De multiplexes and Decodes
Decoder
De Multiplexes
1.There are logic circuit which decodes an input stream from are to another format.
1.It is a Comp nation circuit which router a single input signal to one of reueral output signals.
2.n number of input lines and number of output lines
2. number of select liner and 2n number of output lines.
3.Inverse of Encodes
3.Inverse of Multiplexes
4.In Detection of bits data Encoding
4.In Distribution of the data switching
5.It is used for changing the format of the instruction in the machine specific long
5.It is used on a device to route the data loming from one signal into multiple signals.
6.Majorly implemented in the ret working application.
6.Emploged in data intensive applications where data need changed another form.
6. (a) Explain the working of a full adder circuit with truth table.
Answer:
(a) Explain the working of a full adder circuit with truth table.
The full adder is a little more difficult to implement than a half adder the main difference between a half adder and a full adder is that the full adder has three inputs and two outputs the two inputs are A and B and the third input is a carry input The output carry is designated as and the output is designated a S.
Truth table=>
Input Output
A
B
CIN
COUT
S
0
0
0
0
0
0
0
1
0
1
0
1
0
0
1
0
1
1
1
0
1
0
0
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
The output S is an Ex. OR between the input A and The half adder SUM output B. the will be true only if any of the two inputs out of the three are HIGHT or at logic 1.
This a full adder circuit can be implemented with the help of two half adder circuit the first adder circuit will be used to add A and B to produce a sum the second half adder logic can be used to add to the Sum produced by the first half adder circuit finally the output S is obtained.
If any of the half adder logic producer a carry there will be output carry this will be DR function of the half adder CARRY outputs.
Full adder circuit diagram
(b) How are R-2R ladder used in DACs?
Answer:
How are R-2R ladder used in DACs?
It uses Current law which states that the sum of Current entering a node most be equal to the Sum of the Current leaving a node in the ladder at each note the current is split in half by switching the current into each node the total current flowing is binary weighted.
Using the principle of super postion when you add more current into a resistance the total voltage appearing is the sum of the Voltage by all the individual current i e as each pit is activated so the voltage in creases at the output.
Another claves thing about the R1-R2 ladder and the reason that it works is that if you look to the lift you always see the some impedance :
7. (a) Describe the need of a multiplexer in a system How is a multiplexer different from a decoder? Draw the logic diagram of multiplexer and 2decoder.
Answer:
The very purpose of multiplexing is clearly under stood in its definition only multiple analog sign or digital data stream are combined into One signal Over a shaved medium I e to Humber of electrical Connections/ wireless for transmission of several signals Hence reducing the number of independent inter current
It also simplifies the arrive electronics seduces the cost and pro direct interface with the sim is to share an ex since
Multiplexer
Decoder
1.Multiplexer transmit data.
1. Decodes interprets coded data.
2.Multiplexes is a device which consists of multiple input channels three single line.
2.Decoder consists of multiple inputs passing three multiple output.
3Multiplexes inputs from codes to binary code.
3Decoder binary cusses to inputs.
(b) Explain the working of a S-R flip flop using its logic diagram and truth- table.
Answer:
Explain the working of a S-R flip flop using its logic diagram and truth- table.
SR flip flop operates with only positive clock transition as negative clock transitions where SR loth operates with signals The circuit diagram of SR flip flop is shown.
This circuit has two inputs S&R and two output The operation of SR flip flop affects the output only when positive transition of the clock signal is applied instead of active
Truth Table
S
R
0
0
0
1
0
1
0
1
1
-
Here are present state & next state respectively So SR flip flop can be used for one of these three functions such as hold Reset & set based on the input Conditions when Positive Transition of clock signal is the following table shows the table of SR flip flop.
Present Present Next
Inputs
State
State
S R
0 0
0
0
0 0
1
1
0 1
0
0
0 1
1
0
1 0
0
1
1 0
1
1
1 1
0
1 1
1
8. (a) Explain the counter method for A/D conversion.
Answer:
The Counter type ADC is constricted using a binary counter Digital to analog Counter (DAC) and a Comparator n bit Counts type ADC diagram:-
The output voltage of a DAC is which is equivalent to digital input to DAC is given to the inverting input of the comparator.
The analog input voltage is given to the non-inverting input of the Comparator
The n bit binary counts is initially set to O by using reset Command these fore the digital output is zero and the equivalent voltage is also OV.
When the reset Command is the clock pulses are allowed to go through gate and are counted by the binary comp
The D to A Converter (DAC) converter the digital output to an analog voltage and applied as the inverting input to the comparator
The Output of the Comperator the AND gate to pass the clock
The numbers of clock pules increase with time and the analog input Voltage is a using wave form as shown in below.
The Courting will confine the DAC output equals and just sires more then unknown input voltage
Then the Comparator output becomes low and this disables the AND gate from passing the clock.
The Counting Stops at the instance and at that instant the counts stops its progress and the conversion is said to be complet .
The numbers stored in the n bit counts is the equivalent n bit digital data for the given analog input voltage
(b) Explain D/A conversion in detail.
Answer:
Explain D/A conversion in detail.
A digital to analog (D/A) Converter is a system that converts a digital signal into an analog signal Aa analog to digital Converts (ADC) performs the reverse function
These are several DAC as the suitability of a DAC for a past application is detes mined by figures of including resolution maximum sampling frequency and others Digital to analog conversion can de grade a signal so a DAC should be specified that has insignificant in terms if the application.
DAC are commonly used in music to convert digital data streams into analog audio signals they are also used in televisions and mobile phones to lonest digital video data into analog video signals which connect to the screen drives to display more chrome as color images these two applications use DAC at apposite of the frequency / resolution trade off the audio DAC is low Frequency high frequency type while the video DAC is a high frequency low to mediums resolution type
Do to the components all but the most rpecialized DACs are implemented as into grated circuit (ICS) these typically take the form of metal oxide (MOS) mixed signal integrated circuit that integrate both analog and digital circuit.
Dis crate DACs world typically be externally high speed low resolution power hunger types as used in sada system very high speed test equipment especially sampling Oscillios copes may also use discrete DACs
SECTION-C
9. Attempt all the following:
i. Rewrite the following expression in a form that requires as few inversions as possible:
Answer:
ii. Explain The working of a RS NAND latch.
Answer:
When using static gates as building block the most fun latch is the simple SR latch where S and R stand for set & reset It an be constructed from gates the stored bit is on the output marked .
The circuit shown below is a basic NAND latch the inputs are generally designed for set & Reset respectively because the NAND inputs must mally be logic 1 to avoid affecting the lot action the inputs are considered to be inverted in this circuit.
The circuit feedback to re ember and retain its logical state even after the controlling input signals have changed when the S and R inputs the outputs to the state
iii. Distinguish between complement and duality in Boolean algebra.
Answer:
Duality=> Duality is a phenomenon holiday in a Boolean algebra which means that every identity that involves join and complements gives another when we inter change all the accussences of join and meet for example the absorption lows distriputvity lows and De Morgan’s low’s in pairs of identities which can be by applying duality principle to any of the members of the pairs to obtain the others
Complement=> Complement in a Boolean Algebra is a operation which arrociates to every element ‘n’ a unequal element ‘b’ such that the join of b and b is (the largest element ) and the meet of n and b is o ( the smallest element)
iv. What is the race condition in S-R flip flop? How is it resolved in D-flip flop?
Answer:
when the S and R inputs of an SR flip flop is at logical 1, then the output becomes unstable and its is known as race condition.
v. Draw the circuit diagram of a 8-input multiplexer.
Answer: